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1 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 1. functonal block diagram device features figure 2. package type 20 - lead 4x4 mm qfn ? qfn 4x4mm 20 pin package ? serial & 6 bit parallel interface ? 31.5 db control range 0.5 db step ? no positve glitch ? 2.7 v to 5.25 v supply ? 1.8 v or 3.3 v control logic ? any bit atenuaton error < 0.6 db up to 3ghz ? low inserton loss 0.8db @ 1mhz 0.9 db @ 1ghz 1.3 db @ 2ghz 1.6 db @ 3ghz ? high linearity iip3 > +52 dbm ? input 0.1db compression (p0.1db) 34dbm ? programming modes - direct parallel - latched parallel - serial ? support functon power up state selecton with pup1,2 pin ? stable integral non - linearity over temperature ? low current consumpton 150 a typical ? - 40 c to +105 c operatng temperature ? esd ratng : class2 (2kv hbm) applicaton ? cellular base staton/repeater infrastructure ? digital pre - distorton ? point to point ? test equipment and sensors ? military wireless system ? cable infrastructure ? general purpose wireless product descripton the BDA4601 is a 50? digital step atenuator model which provides adjustable atenuaton from 0 to 31.5 db in 0.5 db steps. the control is a 6 - bit serial interface and parallel interface. covering 1mhz to 4.0 ghz, the inserton loss is less than 1.5 db typi- cal. and ofering the high linearity, low power consumpton, and low inserton loss. the device features safe state transitons with no positve glitch tech- nology. and is optmized for excellent step accuracy the rf input and output are internally matched to 50 and do not require any external matching components. the design is bidirecton- al; therefore, the rf input and output are interchangeable. BDA4601 also features an external negatve supply opton. 1 d 5 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 r f 1 s e r i n c l o c k l e v d d p u p 1 p u p 2 v d d g n d g n d v s s _ e x t / g n d p / s r f 2 d 4 d 3 d 2 g n d d 1 d 0 6 - b i t d i g i t a l s t e p a t t e n u a t o r s e r i a l / p a r a l l e l c o n t r o l l o g i c i n t e r f a c e
2 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 1. device performance _ measured on a berex evaluaton board kit at 25c, 50 ? system, vdd=+3.3v 2. all data has pcb inserton loss de - embedded table 1. electrical specifcatons 1 parameter conditon frequency min typ max unit operatonal frequency range 1 4000 mhz inserton loss 2 atenuaton = 0db 1mhz - 1ghz 0.8 0.9 db > 1 - 2ghz 1.1 1.3 db > 2 - 3ghz 1.3 1.6 db > 3 - 4ghz 2.3 2.8 db atenuaton range 0.5db step 0 - 31.5 db accuracy any bit or bit combinaton 1mhz - 1ghz (0.15 + 1% of atenuaton state) db > 1 - 2.2ghz (0.15 + 2% of atenuaton state) > 2.2 - 3ghz (0.15 + 5% of atenuaton state) > 3 - 4ghz (0.15 + 8% of atenuaton state) return loss input return loss atenuaton = 0db 1 - 2ghz 24 db > 2 - 4ghz 16 output return loss 1 - 2ghz 22 > 2 - 4ghz 15 relatve phase atenuaton = 0db 1ghz 11 degree 2ghz 26 3ghz 30 4ghz 48 input linearity input 0.1db compression point atenuaton = 0db 2140mhz 34 dbm input ip3 pin= +5dbm/tone f = 10khz atn=0.0db rfin =rf1 1950mhz 52 dbm atn=0.0db rfin =rf2 56 atn=15.5db rfin =rf1 57 atn=15.5db rfin =rf2 52 switching tme 50% ctrl to 90% or 10% rf 500 800 ns supply current normal mode 150 180 a bypass mode 50 80 a negatve supply current - 40 - 16 a
3 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 table 3. absolute maximum ratngs operaton of this device above any of these parameters may result in permanent damage. 1 hbm : human body model (jedec jesd22 - a114 ) 2 cdm : charged device model (jedec jesd22 - c101 ) 1 normal mode : connect pin 12 to gnd to enable internal negatve voltage generator 2 bypass mode : do not want to use negatve voltage generator, supply a negatve voltage to vss_ext(pin12) for bypass and disab le internal negatve voltage generator. table 2. recommended operatng conditon parameter symbol conditon min typ max unit supply voltages normal mode 1 supply voltage v dd 2.7 5.5 v bypass mode 2 supply voltage v dd 2.7 5.5 v negatve supply voltage v ss_ext - 3.6 - 3.0 v digital control input normal mode or bypass mode input voltage v ctl p/s, clk, serin, le, d0 - d5, pup1,pup2 high v ctlh v dd =3.3v/5v 1.17 3.6 v low v ctll v dd =3.3v/5v 0 0.6 v operatng temperature range t case exposed paddle - 40 105 ? c rf cw input power p in_cw rf1 or rf2 24 dbm impedance z load single ended 50 parameter symbol min typ max unit supply voltage v dd - 0.3 5.5 v digital input voltage v ctl - 0.3 3.6 v maximum input power p in_cwmax 34 dbm temperature jucton t j 140 storage t st - 65 150 refow t r 260 esd sensitvity hbm 1 esd hbm 2000 (class 2) v cdm 2 esd cdm 500 (class c2) v
4 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 table 4. pin descripton figure 3. pin confguraton(top view) * device is rf bi - directonal pin pin name descripton 1 d5 parallel control voltage inputs, atenuaton control bit 16db 2 rf1 1 rf1 port (atenuator rf input) this pin can also be used as an output because the design is bidirectonal. rf1 is dc - coupled and matched to 50 3 serin serial interface data input 4 clk serial interface clock input 5 le latch enable input 6 v dd power supply (nominal 3.3v) 7 pup1 power - up state selecton bits. these pins set the atenuaton value at power - up (see table 9). there is no internal pull - up or pull - down resistor on these pins; therefore, they must always be kept at a valid logic level ( v ctlh or v ctll ) and not be lef foatng 8 pup2 9 v dd supply voltage (nominal 3.3v) 12 v ss_ext 2 / gnd external v ss negatve voltage control or ground do not want to use negatve voltage supply, these pins must be connected to ground (gnd, default setng is gnd) 13 p/s parallel/serial mode select. for parallel mode operaton, set this pin to low. for serial mode operaton, set this pin to hig h. 14 rf2 1 rf2 port (atenuator rf output.) this pin can also be used as an input because the design is bidirectonal. rf2 is dc - coupled and matched to 50 . 15 d4 parallel control voltage inputs, atenuaton control bit 8db 16 d3 parallel control voltage inputs, atenuaton control bit 4db 17 d2 parallel control voltage inputs, atenuaton control bit 2db 19 d1 parallel control voltage inputs, atenuaton control bit 1db 20 d0 parallel control voltage inputs, atenuaton control bit 0.5db pad gnd exposed pad: the exposed pad must be connected to ground for proper operaton 10,11,18 gnd ground, these pins must be connected to ground note: 1. rf pins 2 and 14 must be at 0v dc. the rf pins do not require dc blocking capacitors for proper operaton if the 0v dc req uir ement is met 2. connect vssext (pin 12, vssext = gnd) to enable internal negatve voltage generator 1 d 5 e x p o s e d p a d 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 r f 1 s e r i n c l o c k l e v d d p u p 1 p u p 2 v d d g n d g n d v s s _ e x t / g n d p / s r f 2 d 5 d 3 d 2 g n d d 1 d 0
5 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 programming optons figure 4. serial mode resister timing diagram table 8. truth table for serial control word BDA4601 can be programmed using either the parallel or serial inter- face, which is selectable via p/s pin(pin13). serial mode is selected by foatng p/s or pulling it to a voltage logic low and parallel mode is selected by setng p/s to logic low serial control mode the serial interface is a 6 bit shif register to shif in the data msb (d5) frst. when serial programming is used, all the parallel control input pins (1, 15, 16, 17, 19, 20) must be grounded. it is controlled by three cmos - compatble signals: serin, clock, and latch enable (le). table 5. 6 - bit serial word sequence d5 atenuaton 16db control bit d4 atenuaton 8db control bit d3 atenuaton 4db control bit d2 atenuaton 2db control bit d1 atenuaton 1db control bit d0 atenuaton 0.5db control bit table 7. serial interface timing specifcatons symbol parameter min typ max unit f clk serial data clock frequency 10 mhz t sck minimum serial period 70 t cs control setup tme 30 t ch control hold tme 30 t ln le setup tme 10 t lew minimum le pulse width 10 t les minimum le pulse width 600 t ckn serial clock hold tme from le 10 the BDA4601 has a 3 - wire serial peripheral interface (spi): serial data input (data), clock (clk), and latch enable (le). the se rial control inter- face is actvated when p/s is set to high. in serial mode, the 6 - bit data is clocked msb frst on the rising clk edges into the shif register and then le must be toggled high to latch the new atenuaton state into the device. le must be set to low to clock new 6 - bit data into the shif register because clk is mask ed to prevent the atenuator value from changing if le is kept high (see figure 4 and table 8). digital control input atenuaton d5 d4 d3 d2 d1 d0 (msb) (lsb) (db) high high high high high high 0 (reference) high high high high high low 0.5 high high high high low high 1 high high high low high high 2 high high low high high high 4 high low high high high high 8 low high high high high high 16 low low low low low low 31.5 p/s control mode low parallel high serial table 6. mode selecton d 5 x x d [ 5 : 0 ] n e x t w o r d x d 4 d 3 d 2 d 1 d 0 x t c h t c s t s c k t l n t l e w t c k n t l e s m s b [ f i r s t i n ] l s b [ l a s t i n ] p / s s e r i a l i n c l k l e
6 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 5. latched parallel mode timing diagram parallel control mode the BDA4601 has six digital control inputs, d0 (lsb) to d5 (msb), to select the desired atenuaton state in parallel mode, as shown in table 6. the parallel control interface is actvated when p/s is set to low. there are two modes of parallel operaton: direct parallel and latched parallel direct parallel mode the le pin must be kept low. the atenuaton state is changed by the control voltage inputs (d0 to d5) directly. this mode is ideal for man- u a l c o n t r o l o f t h e a t e n u a t o r . i n t h i s m o d e t h e d e v i c e w i l l i m m e d i a t e- ly react to any voltage changes to the parallel control pins [pins 1, 15, 16, 17,19, 20]. use direct parallel mode for the fastest setling tme. latched parallel mode the le pin must be kept low when changing the control voltage inputs (d0 to d5) to set the atenuaton state. when the desired state is set, le must be toggled low to transfer the 6 - bit data to the bypass switches of the atenuator array, and then toggled low to latch the change into the device untl the next desired atenuaton change (see figure 5 and table 8). table 10. pup truth table table 9. parallel interface timing specifcatons symbol parameter min typ max unit t lew minimum le pulse width 10 ns t ph data hold tme from le 10 ns t ps data setup tme to le 10 ns power - up interface the BDA4601 uses the pup1 and pup2 control voltage inputs to set the atenuaton value to a known value at power - up before the inital control data word is provided in either serial or parallel mode. when the atenuator powers up with le set to low, the state of pup1 and pup2 determines the power - up state of the device per the truth table shown in table 9. the atenuator latches in the desired power - up state approximately 200 ms afer power - up. atenuaton state p/s le pup1 pup2 31.5 db low low high high 16 db low low high low 8 db low low low high reference loss low low low low defned by c0.5 - c16 low high don t care don t care d0 d1 d2 d3 d4 d5 attenuation state le p/s low low low low low low reference loss high low high low low low low low 0.5db high low low high low low low low 1db high low low low high low low low 2db high low low low low high low low 4db high low low low low low high low 8db high low low low low low low high 16db high low high high high high high high 31.5db high low table 8. truth table for the parallel control word x t p h t p s p / s p a r a l l e l i n l e x d [ 5 : 0 ] p a r a l l e l c o n t r o l t l e w x
7 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 6. inserton loss vs. frequency over major atenuaton states figure 7 inserton loss vs. frequency over temperature figure 8. input return loss vs. frequency over major atenuaton states figure 10. output return loss vs. frequency over major atenuaton states figure 9. input return loss vs. frequency over temperature figure 11. output return loss vs. frequency over temperature typical performance data @ 25and v dd = 3.3v, all data has pcb inserton loss de - embedded, unless otherwise noted typical rf performance plot - BDA4601 evk - pcb -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 0 1 2 3 4 insertion loss [db] frequency [ghz] +25c -40c +105c -40 -35 -30 -25 -20 -15 -10 -5 0 0 1 2 3 4 insertion loss [db] frequency [ghz] 0db 0.5db 1db 2db 4db 8db 16db 31.5db -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 input return loss [db] frequency [ghz] 0db 0.5db 1db 2db 4db 8db 16db 31.5db -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 input return loss [db] frequency [ghz] +25c -40c +105c -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 output return loss [db] frequency [ghz] 0db 0.5db 1db 2db 4db 8db 16db 31.5db -60 -50 -40 -30 -20 -10 0 0 1 2 3 4 output return loss [db] frequency [ghz] +25c -40c +105c
8 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 12. atenuaton error vs. atenuaton state over frequency figure13. atenuaton error vs. major frequency over atenuaton states figure 14. step error vs atenuaton state over frequency figure 16. relatve phase vs. atenuaton state over frequency figure 15. actual atenuaton vs ideal atenuaton over frequency figure 17. atenuaton error at 100mhz vs temperature over atenuaton state typical performance data @ 25and v dd = 3.3v, all data has pcb inserton loss de - embedded, unless otherwise noted typical rf performance plot - BDA4601 evk - pcb -3 -2 -1 0 1 2 3 0 1 2 3 4 attenuation error [db] frequency [ghz] 0.5db 1db 2db 4db 8db 16db 31.5db -10 0 10 20 30 40 50 60 0 1 2 3 4 relative phase [degree] frequency [ghz] 0.5db 1db 2db 4db 8db 16db 31.5db -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 5 10 15 20 25 30 attenuation error [db] attenuation setting [db] +25c -40c +105c -3 -2 -1 0 1 2 3 0 5 10 15 20 25 30 attenuation error [db] attenuation setting [db] 10mhz 100mhz 1ghz 2ghz 3ghz 4ghz -1 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1 0 5 10 15 20 25 30 step attenuation error [db] attenuation setting [db] 10mhz 100mhz 1ghz 2ghz 3ghz 4ghz 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 attenuation error [db] attenuation setting [db] 10mhz 100mhz 1ghz 2ghz 3ghz 4ghz
9 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 18. atenuaton error at 1ghz vs temperature over atenuaton state figure 19. atenuaton error at 2ghz vs temperature over atenuaton state figure 20. atenuaton error at 3ghz vs temperature over atenuaton state figure 22. compression 3 at 2.14ghz vs. input power over major atenuaton state figure 21. atenuaton error at 4ghz vs temperature over atenuaton state figure 23. compression at 2.14ghz and minimum atenuaton state 1 vs. input power over temperature typical performance data @ 25and v dd = 3.3v, all data has pcb inserton loss de - embedded, unless otherwise noted typical rf performance plot - BDA4601 evk - pcb note: 1. minimum atenuaton state means that the atenuaton setng is 0db. 2. maximum atenuaton state means that the atenuaton setng is 31.5db. 3. input 0.1db compression -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 5 10 15 20 25 30 attenuation error [db] attenuation setting [db] +25c -40c +105c -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 5 10 15 20 25 30 attenuation error [db] attenuation setting [db] +25c -40c +105c -2 -1.5 -1 -0.5 0 0.5 1 1.5 2 0 5 10 15 20 25 30 attenuation error [db] attenuation setting [db] +25c -40c +105c -4 -3 -2 -1 0 1 2 0 5 10 15 20 25 30 attenuation error [db] attenuation setting [db] +25c -40c +105c -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 20 22 24 26 28 30 32 34 compression [db] input power[dbm] +25c -40c +105c -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 20 22 24 26 28 30 32 34 compression [db] input power[dbm] 0db 15.5db 31.5db
10 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 24. compression 2 at 2.14ghz and maximum atenuaton state 1 vs. input power over temperature typical performance data @ 25and v dd = 3.3v, all data has pcb inserton loss de - embedded, unless otherwise noted typical rf performance plot - BDA4601 evk - pcb figure 25. iip3 at 1.8ghz vs. atenuaton setng over temperature figure 26. iip3 at 1.95ghz vs. atenuaton setng over temperature figure 28. iip3 at 2.45ghz vs. atenuaton setng over temperature figure 27. iip3 at 2.15ghz vs. atenuaton setng over temperature note: 1. maximum atenuaton state means that the atenuaton setng is 31.5db. 2. input 0.1db compression figure 28. iip3 at 2.65ghz vs. atenuaton setng over temperature -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 20 22 24 26 28 30 32 34 compression [db] input power[dbm] +25c -40c +105c 10 20 30 40 50 60 70 0.0 5.0 10.0 15.0 20.0 25.0 30.0 iip3 [db] attenuation setting [db] +25c -40c +105c 10 20 30 40 50 60 70 0.0 5.0 10.0 15.0 20.0 25.0 30.0 iip3 [db] attenuation setting [db] +25c -40c +105c 10 20 30 40 50 60 70 0.0 5.0 10.0 15.0 20.0 25.0 30.0 iip3 [db] attenuation setting [db] +25c -40c +105c 10 20 30 40 50 60 70 0.0 5.0 10.0 15.0 20.0 25.0 30.0 iip3 [db] attenuation setting [db] +25c -40c +105c 10 20 30 40 50 60 70 0.0 5.0 10.0 15.0 20.0 25.0 30.0 iip3 [db] attenuation setting [db] +25c -40c +105c
11 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 BDA4601 evaluaton board kit descripton evaluaton board kit introducton BDA4601 evaluaton kit is made up of a combinaton of an rf board and an interface board the schematc of the BDA4601 evaluaton rf board is shown in figure 30. the BDA4601 evalu- a t o n r f b o a r d i s c o n s t r u c t e d o f a 4 - l a y e r m a t e r i a l w i t h a c o p p e r t h i c k n e s s o f 0 . 7 m i l o n e a c h layer. every copper layer is separated with a dielectric material. the top dielectric material is 12 mil ro4003. the middle and botom dielectric materials are fr - 4, used for mechanical strength and overall board thickness of approximately 1.55mm. BDA4601 evaluaton interface board is assembled with a sp3t switches(d1~d6,le), sp2t mechanical switch (p/s), and several header & switch. evaluaton board programming using usb interface in order to evaluate the BDA4601 performance, the applicaton sofware has to be installed on your computer. and the dsa applicaton sofware gui supports latched parallel and serial modes . sofware can be downloaded from berex s website serial control mode ? connect directly the evaluaton intefrace board usb port(j3) to pc ? set the directon of p< - >s switch to s directon ? set the d0~d5,le switch to the central positon. ? operate the 0~31.5db atenuaton state in gui and then control the dsa latched parallel control mode ? connect directly the evaluaton intefrace board usb port(j3) to pc ? set the directon of p< - >s switch to p directon ? set the d0~d5,le switch to the middle positon. ? operate the 0~31.5db atenuaton state in gui and then control the dsa direct parallel control mode ? set the directon of p< - >s switch to p directon ? set le switch to the low positon ? for the setng to atenuaton state, d0~d5 switches can be combined in manually pro- gram, refer to table 8. please refer to user manual for more detailed operaton method of BDA4601 evk. figure 30. BDA4601 evk
12 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 31. evaluaton board schematc diagram figure 33. evaluaton board pcb layer informaton 50 figure 32. evaluaton board pcb layout informaton 50 table11. bill of material - evaluaton board no. ref des part qty value descripton remark 1 c1,c3,c5 - c10 8 100pf cap, 0402, chip ceramic, 0.25% 2 c2,c4 2 100nf cap, 0402, chip ceramic, 0.25% 3 r1,r2 2 10k ohm res, 0402, chip, 5% 4 r3,r4 2 nc 5 r5,r6,r7,r16,r17 5 0 ohm res, 0402, chip, 5% 6 c41 1 10 uf tantal 3216 10uf 16v 7 j1,j2 2 con sma end launch 8 u1 1 chip dsa, BDA4601 qfn4x4 24l BDA4601 evaluaton board kit descripton note: 1. c2 and c3 should be placed near the device. c o p p e r : 1 o z ( 0 . 0 3 5 m m ) , t o p l a y e r r o 4 0 0 3 c : 0 . 3 0 5 m m c o p p e r : 1 o z ( 0 . 0 3 5 m m ) , g n d , i n n e r l a y e r c o p p e r : 1 o z ( 0 . 0 3 5 m m ) , i n n e r l a y e r c o p p e r : 1 o z ( 0 . 0 3 5 m m ) , b o t t o m l a y e r f r - 4 : 0 . 3 6 m m c o r e f r - 4 : 0 . 7 3 m m f i n i s h t h i c k n e s s : 1 . 5 5 t t o p b o t t o m r o 4 0 0 3 c e r : 3 . 3 8 f r - 4 e r : 4 . 5 ~ 4 . 8 f r - 4 e r : 4 . 5 ~ 4 . 8 u 1 ( b d a 4 6 0 1 ) r f 1 1 2 3 4 5 6 7 8 9 1 0 1 5 1 4 1 3 1 2 1 1 2 0 1 9 1 8 1 7 1 6 v d d c 8 / c l k c 1 6 / d a t a r f 2 c 4 c 1 c 2 c 0 . 5 p / s p u p 1 p u p 2 r 1 1 0 k r 1 7 0 o h m c 4 1 1 0 u f c 3 1 0 0 n f c 2 1 0 0 p f c 1 1 0 0 p f c 1 0 1 0 0 p f c 6 1 0 0 p f c 7 1 0 0 p f c 8 1 0 0 p f c 9 1 0 0 p f r 1 6 0 o h m c 4 1 0 0 p f c 5 1 0 0 n f r 3 n c r 5 0 o h m r 6 0 o h m r 4 n c r 2 1 0 k v s s / g n d j 1 j 2 r 7 0 o h m
13 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 34. packing outline dimension figure 35. recommend land patern
14 preliminary datasheet rev. 0.1 berex website: www.berex.com email: sales@berex.com specifcatons and informaton are subject to change and products may be discontnued without notce. berex is a trademark o f b erex. all other trademarks are the property of their respectve owners. ? 2018 berex 6bit digital step atenuator 1mhz C 4ghz BDA4601 figure 36. tape & reel lead platng fnish 100% tin mate fnish (all berex products undergoes a 1 hour, 150 degree c, anneal bake to eliminate thin whisker growth concerns.) msl / esd ratng esd ratng: value: test: standard: msl ratng: standard: class 2 passes 2000v human body model(hbm) jedec standard jesd22 - a114b level 1 at +265c convecton refow jedec standard j - std - 020 nato cage code: 2 n 9 6 f figure 37. package marking packaging informaton: tape width 12mm reel size 7 inch device cavity pitch 8mm devices per reel 1k marking informaton: BDA4601 device name yy year ww work week xx lot number b d a 4 6 0 1 y y w w x x p r o p e r e s d p r o c e d u r e s s h o u l d b e f o l l o w e d w h e n h a n d l i n g t h i s d e v i c e . c a u t i o n : e s d s e n s i t i v e a p p r o p r i a t e p r e c a u t i o n s i n h a n d l i n g , p a c k a g i n g a n d t e s t i n g d e v i c e s m u s t b e o b s e r v e d .

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